NOTICE OF INTENT TO SOLE SOURCE All-Glass Microwave Microfluidic Wafers

The National Institute of Standards and Technology (NIST) Acquisition Management Division on behalf of the Communications Technology Laboratory, RF Technology Division intends to negotiate with Mosaic Microsystems LLC on a sole source basis under the authority of FAR Subpart 13.106-1(b), soliciting from a single source, for the acquisition of All-Glass Microwave Microfluidic Wafers referenced herein.

Specific Requirements:

Item Specifications and Quantities:

Item 1: Encapsulated All-Glass Microwave Microfluidic Wafers (8-inch wafers) Quantity:

4 EA

Specifications: 1.1 High purity fused silica for substrate and microfluidic roof wafers. 1.2 One platinum resistor deposition layer (25 nm) on substrate wafer. 1.3 One platinum conductor deposition layer (600 nm) on top of the resistor layer. 1.4 Platinum layers shall be adhered with non-magnetic adhesion layers. 1.5 Metallization layer tolerances of 0.5 microns.

1.6 One patterned silicon dioxide layer (1-5 microns thick) on top of platinum electrode layer, polished with chemical-mechanical polishing to required smoothness of RMS less than or equal to 1 nm. 1.7 Silicon dioxide layer shall be adhered to the platinum electrode layer with silicon nitride. 1.8 All patterns will be provided by NIST as .gds files. 1.9 Hermetically bonded glass channels to substrate wafer, 100-micron depth channels.

1.10 Channels shall have straight sidewalls achieved through, for example, laser cutting. 1.11 Platinum electrodes must be directly exposed to the channel. 1.12 Platinum electrode ends (at least 500 microns width) must be fully exposed for probe station measurements. 1.13 Any etching for exposure of platinum electrodes must not exceed an over-etch of 50 nm below the substrate surface. 1.14 Temperature treatments of wafers in process should not exceed 300 degrees Celsius.

1.15 Channel to substrate misalignment tolerance of 10 microns. 1.16 Devices should withstand 100 psi applied fluid pressure. 1.17 Vias to the fluid channels should come through the top wafer (the wafer with channel etched out). 1.18 Wafers should be fully diced into individual chips.

Item 2: Fused Silica Wafers with Calibration Artifacts (8-inch wafers) Quantity: 1 EA

2.1 High purity fused silica for substrate wafer. 2.2 One platinum resistor deposition layer (25 nm) on substrate wafer. 2.3 One platinum conductor deposition layer (600 nm) on top of the resistor layer. 2.4 Platinum layers shall be adhered with non-magnetic adhesion layers. 2.5 Metallization layer tolerances of 0.5 microns.

2.6 One patterned silicon dioxide layer (1-5 microns thick) on top of platinum electrode layer, polished with chemical-mechanical polishing to required smoothness of RMS less than or equal to 1 nm. 2.7 Silicon dioxide layer shall be adhered to the platinum electrode layer with silicon nitride. 2.8 All patterns will be provided by NIST as .gds files. 2.9 Platinum electrode ends (at least 500 microns width) must be fully exposed for probe station measurements.

2.9 Any etching for exposure of platinum electrodes must not exceed an over-etch of 50 nm below the substrate surface. 2.10 Wafer should be fully diced into individual chips. NAICS Code is 334413 - Semiconductor and Related Device Manufacturing, with a Size Standard of 1250 Employees. NIST anticipates negotiating and awarding a firm-fixed-price purchase order to Mosaic Microsystems for this requirement.

JUSTIFICATION FOR OTHER THAN FULL AN OPEN COMPETITION: Market research resulted in Mosaic Microsystems LLC being the only vendor to align and hermetically seal microwave coplanar waveguides into all-glass microfluidic channels. Mosaic Microsystems was the only company to fulfill the technical specifications laid out in that procurement and developed a specialized wafer alignment process to meet the needs of the procurement.

No other manufacturers are known to produce the proprietary wafer bonding technology to create the hermetic seals at low enough temperatures and pressures to avoid deforming the embedded microwave circuitry. Interested parties that can demonstrate they could satisfy the requirement listed above for NIST must clearly and unambiguously identify their capability to do so in writing on or before the response date for this notice. This notice of intent is not a solicitation.

Information submitted in response to this notice will be used solely to determine whether competitive procedures could be used for this acquisition. If competitive procedures are not used, it is estimated that an award will be issued 4th Quarter FY24. Any questions regarding this notice must be submitted in writing via email to clifford.nicholson@nist.gov. All responses to this notice of intent must be submitted to clifford.nicholson@nist.gov no later than 6/29/2024 at 10:00 a.m. MDT.